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4 RON, Triple/Quad SPDT 15 V/+12 V/5 V iCMOS(R) Switches ADG1433/ADG1434
FEATURES
4.7 maximum on resistance @ 25C 0.5 on resistance flatness 33 V supply maximum ratings Fully specified at 15 V/+12 V/5 V 3 V logic compatible inputs Rail-to-rail operation Break-before-make switching action 16-/20-lead TSSOP and 4 mm x 4 mm LFCSP_VQ packages
FUNCTIONAL BLOCK DIAGRAMS
ADG1433
S1A D1 S1B S3B D3 S2B D2 S2A LOGIC S3A
APPLICATIONS
Relay replacement Audio and video routing Automatic test equipment Data acquisition systems Temperature measurement systems Avionics Battery-powered systems Communication systems Medical equipment
IN1 IN2 IN3 EN SWITCHES SHOWN FOR A "1" INPUT LOGIC.
06181-001
Figure 1. ADG1433 TSSOP and LFCSP_VQ
ADG1434
S1A D1 S1B IN1 IN2 S2B D2 S2A S4A D2 S4B IN4 S2B IN3 S3B D3 S3A D2 S2A S1A D1 S1B
ADG1434
S4A D2 S4B S3B D3 S3A LOGIC
06181-002
SWITCHES SHOWN FOR A "1" INPUT LOGIC.
SWITCHES SHOWN FOR A "1" INPUT LOGIC.
Figure 2. ADG1434 TSSOP
Figure 3. ADG1434 LFCSP_VQ
GENERAL DESCRIPTION
The ADG1433 and ADG1434 are monolithic industrial-CMOS (iCMOS) analog switches comprising three independently selectable single-pole, double-throw (SPDT) switches and four independently selectable SPDT switches, respectively. All channels exhibit break-before-make switching action that prevents momentary shorting when switching channels. An EN input on the ADG1433 (LFCSP and TSSOP packages) and ADG1434 (LFCSP package only) is used to enable or disable the device. When disabled, all channels are switched off. The iCMOS modular manufacturing process combines high voltage, complementary metal-oxide semiconductor (CMOS) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow on resistance and on resistance flatness of these switches make them ideal solutions for data acquisition and gain switching applications, where low distortion is critical. iCMOS construction ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1. 2. 3. 4. 4.7 maximum on resistance. 0.5 on resistance flatness. 3 V logic compatible digital input VIH = 2.0 V, VIL = 0.8 V. 16-/20-lead TSSOP and 4 mm x 4 mm LFCSP_VQ packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
06181-101
IN1 IN2 IN3 IN4 EN
ADG1433/ADG1434 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagrams............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 15 V Dual Supply.......................................................................... 3 12 V Single Supply........................................................................ 5 5 V Dual Supply............................................................................ 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance .......................................................................7 ESD Caution...................................................................................7 Pin Configurations and Function Descriptions ............................8 ADG1433........................................................................................8 ADG1434........................................................................................9 Typical Performance Characteristics ........................................... 10 Test Circuits..................................................................................... 13 Terminology .................................................................................... 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 17
REVISION HISTORY
10/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADG1433/ADG1434 SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Drain Off Leakage, ID (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANS Break-Before-Make Time Delay, tD tON(EN) tOFF(EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion, THD + N -3 dB Bandwidth Insertion Loss CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD IDD +25C -40C to +85C -40C to +125C 1 VSS to VDD 4 4.7 0.5 0.78 0.5 0.72 0.04 0.3 0.04 0.3 0.05 0.4 5.7 0.85 0.77 6.7 1.1 0.92 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max A typ A max Test Conditions/Comments
VS = 10 V, IS = -10 mA; see Figure 25 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -10 mA VS = 10 V, IS = -10 mA VDD = +16.5 V, VSS = -16.5 V VD = 10 V, VS = 10 V; see Figure 26 VD = 10 V, VS = 10 V; see Figure 26 VS = VD = 10 V; see Figure 27
0.6 0.6 0.8
3 3 8 2.0 0.8
0.005 0.1 3 140 170 40 140 170 60 75 -50 -70 -70 0.025 200 0.24 12 22 72 0.001 1 260 440
Rev. 0 | Page 3 of 20
VIN = VGND or VDD
200
230 30
200 85
230 90
RL = 100 , CL = 35 pF VS = 10 V, see Figure 28 RL = 100 , CL = 35 pF VS1 = VS2 = 10 V; see Figure 29 RL = 100 , CL = 35 pF VS = 10 V, see Figure 30 RL = 100 , CL = 35 pF VS = 10 V; see Figure 30 VS = 0 V, RS = 0 , CL = 1 nF, see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 32 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 34 RL = 110 , 15 V p-p, f = 20 Hz to 20 kHz, see Figure 35 RL = 50 , CL = 5 pF, see Figure 33 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 33 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V
ADG1433/ADG1434
Parameter ISS VDD/VSS
1 2
+25C 0.001
-40C to +85C
-40C to +125C 1 1 4.5/16.5
Unit A typ A max V min/max
Test Conditions/Comments Digital inputs = 0 V, 5 V, or VDD GND = 0 V
Temperature range for Y version: -40C to +125C. Guaranteed by design, not subject to production test.
Rev. 0 | Page 4 of 20
ADG1433/ADG1434
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On Resistance Match Between Channels, RON On Resistance Flatness, RFLAT(ON) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Drain Off Leakage, ID (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANS Break-Before-Make Time Delay, tD tON(EN) tOFF(EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth Insertion Loss CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD IDD VDD
1 2
+25C
-40C to +85C
-40C to +125C 1 0 to VDD
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ MHz typ dB typ pF typ pF typ pF typ A typ A max A typ A max V min/max
Test Conditions/Comments
6 8 0.55 0.82 1.5 2.5 0.04 0.3 0.04 0.3 0.06 0.4
9.5 0.85 2.5
11.2 1.1 2.8
VS = 0 V to 10 V, IS = -10 mA, see Figure 25 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -10 mA VS = 0 V to 10 V, IS = -10 mA VDD = 13.2 V VS = 1 V/10 V, VD = 10 V/1 V, see Figure 26 VS = 1 V/10 V, VD = 10 V/1 V, see Figure 26 VS = VD = 1 V or 10 V, see Figure 27
0.6 0.6 0.8
3 3 8 2.0 0.8
0.005 0.1 4 200 255 80 210 270 70 86 -10 -70 -70 135 0.5 25 45 80 0.002 1 260 440 5/16.5
VIN = VGND or VDD
310
350 55
320 95
360 105
RL = 100 , CL = 35 pF VS = 8 V, see Figure 28 RL = 100 , CL = 35 pF VS1 = VS2 = 8 V, see Figure 29 RL = 100 , CL = 35 pF VS = 8 V, see Figure 30 RL = 100 , CL = 35 pF VS = 8 V, see Figure 30 VS = 6 V, RS = 0 , CL = 1 nF, see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 32 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 34 RL = 50 , CL = 5 pF, see Figure 33 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 33 f = 1 MHz f = 1 MHz f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V VSS = 0 V, GND = 0 V
Temperature range for Y version: -40C to +125C. Guaranteed by design, not subject to production test.
Rev. 0 | Page 5 of 20
ADG1433/ADG1434
5 V DUAL SUPPLY
VDD = +5 V 10%, VSS = -5 V 10%, GND = 0 V, unless otherwise noted. Table 3.
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Drain Off Leakage, ID (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 2 Transition Time, tTRANS Break-Before-Make Time Delay, tD tON(EN) tOFF(EN) Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion, THD + N -3 dB Bandwidth Insertion Loss CS (OFF) CD (OFF) CD, CS (ON) POWER REQUIREMENTS IDD ISS VDD/VSS
1 2
+25C
-40C to +85C
-40C to +125C 1 VSS to VDD
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns min ns typ ns max ns typ ns max pC typ dB typ dB typ % typ MHz typ dB typ pF typ pF typ pF typ A typ A max A typ A max V min/max
Test Conditions/Comments
7 9 0.55 0.78 1.5 2.5 0.02 0.3 0.02 0.3 0.04 0.4
10.5 0.91 2.5
12 1.1 3
VS = 4.5 V, IS = -10 mA, see Figure 25 VDD = +4.5 V, VSS = -4.5 V VS = 4.5 V, IS = -10 mA VS = 4.5 V, IS = -10 mA VDD = +5.5 V, VSS = -5.5 V VD = 4.5 V, VS = 4.5 V, see Figure 26 VD = 4.5 V, VS = 4.5 V, see Figure 26 VS = VD = 4.5 V, see Figure 27
0.6 0.6 0.8
3 3 8 2.0 0.8
0.005 0.1 4 315 430 90 325 425 150 200 -10 -70 -70 0.06 145 0.5 18 32 80 0.002 1 0.001 1 4.5/16.5
VIN = VGND or VDD
480
550 55
490 225
545 240
RL = 100 , CL = 35 pF VS = 5 V, see Figure 28 RL = 100 , CL = 35 pF VS1 = VS2 = 5 V, see Figure 29 RL = 100 , CL = 35 pF VS = 5 V, see Figure 30 RL = 100 , CL = 35 pF VS = 5 V, see Figure 30 VS = 0 V, RS = 0 , CL = 1 nF, see Figure 31 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 32 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 34 RL = 110 , 5 V p-p, f = 20 Hz to 20 kHz, see Figure 35 RL = 50 , CL = 5 pF, see Figure 33 RL = 50 , CL = 5 pF, f = 1 MHz, see Figure 33 f = 1 MHz f = 1 MHz f = 1 MHz VDD = +5.5 V, VSS = -5.5 V Digital inputs = 0 V, 5 V, or VDD Digital inputs = 0 V, 5 V, or VDD GND = 0 V
Temperature range for Y version: -40C to +125C. Guaranteed by design, not subject to production test. Rev. 0 | Page 6 of 20
ADG1433/ADG1434 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 4.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs, Digital Inputs1 Continuous Current, S or D Peak Current, S or D (Pulsed at 1 ms, 10% Duty Cycle Maximum) Operating Temperature Range Industrial (Y Version) Storage Temperature Range Junction Temperature Reflow Soldering Peak Temperature (Pb-Free)
1
THERMAL RESISTANCE
Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 30 mA 100 mA
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance
Package Type TSSOP LFCSP_VQ JA 150.4 30.4 JC 50 - Unit C/W C/W
ESD CAUTION
-40C to +125C -65C to +150C 150C 260 (+ 0 to -5)C
Overvoltages at A, EN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.
Rev. 0 | Page 7 of 20
ADG1433/ADG1434 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG1433
15 VDD 14 GND 16 S1A
VDD 1 S1A 2 D1 3 S1B 4 S2B 5 D2 6 S2A 7 IN2 8
16 15
GND IN1 EN VSS S3B D3 S3A IN3
06181-003
ADG1433
TOP VIEW (Not to Scale)
14 13 12 11 10 9
D1 1 S1B 2 S2B 3 D2 4
PIN 1 INDICATOR
13 IN1
12 EN 11 VSS 10 S3B 9 D3
06181-005
ADG1433
TOP VIEW (Not to Scale)
Figure 4. TSSOP Pin Configuration
Figure 5. LFCSP_VQ Pin Configuration
Table 6. ADG1433 Pin Function Descriptions
Pin Number TSSOP LFCSP_VQ 1 15 2 16 3 1 4 2 5 3 6 4 7 5 8 6 9 7 10 8 11 9 12 10 13 11 14 12 15 16 13 14 Mnemonic VDD S1A D1 S1B S2B D2 S2A IN2 IN3 S3A D3 S3B VSS EN IN1 GND Description Most Positive Power Supply Potential. Source Terminal 1A. Can be an input or an output. Drain Terminal 1. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Source Terminal 2B. Can be an input or an output. Drain Terminal 2. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Logic Control Input. Logic Control Input. Source Terminal 3A. Can be an input or an output. Drain Terminal 3. Can be an input or an output. Source Terminal 3B. Can be an input or an output. Most Negative Power Supply Potential. In single supply applications, it can be connected to ground. Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx logic inputs determine the on switches. Logic Control Input. Ground (0 V) Reference.
Table 7. ADG1433 Truth Table
EN 1 0 0 INx X 0 1 SxA Off Off On SxB Off On Off
Rev. 0 | Page 8 of 20
S3A 8
S2A 5
IN3 7
IN2 6
ADG1433/ADG1434
ADG1434
S1A 2 D1 3 S1B 4 VSS 5 GND 6 S2B 7 D2 8 S2A 9 IN2 10
19 18
S4A D4 S4B VDD NC S3B D3
ADG1434
TOP VIEW (Not to Scale)
17 16 15 14 13 12 11
D1 S1B VSS GND S2B
1 2 3 4 5
20 19 18 17 16
PIN 1 INDICATOR
S1A IN1 EN IN4 S4A
IN1 1
20
IN4
ADG1434
TOP VIEW (Not to Scale)
15 14 13 12 11
D4 S4B VDD S3B D3
IN3
06181-004
NC = NO CONNECT
Figure 7. LFCSP_VQ Pin Configuration
Figure 6. TSSOP Pin Configuration
Table 8. ADG1434 Pin Function Descriptions
Pin Number TSSOP LFCSP_VQ 1 19 2 20 3 1 4 2 5 3 6 4 7 5 8 6 9 7 10 8 11 9 12 10 13 11 14 12 15 - 16 13 17 14 18 15 19 16 20 17 - 18 Mnemonic IN1 S1A D1 S1B VSS GND S2B D2 S2A IN2 IN3 S3A D3 S3B NC VDD S4B D4 S4A IN4 EN Description Logic Control Input. Source Terminal 1A. Can be an input or an output. Drain Terminal 1. Can be an input or an output. Source Terminal 1B. Can be an input or an output. Most Negative Power Supply Potential. In single supply applications, it can be connected to ground. Ground (0 V) Reference. Source Terminal 2B. Can be an input or an output. Drain Terminal 2. Can be an input or an output. Source Terminal 2A. Can be an input or an output. Logic Control Input. Logic Control Input. Source Terminal 3A. Can be an input or an output. Drain Terminal 3. Can be an input or an output. Source Terminal 3B. Can be an input or an output. No Connect. Most Positive Power Supply Potential. Source Terminal 4B. Can be an input or an output. Drain Terminal 4. Can be an input or an output. Source Terminal 4A. Can be an input or an output. Logic Control Input. Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx logic inputs determine the on switches.
Table 9. ADG1434 TSSOP Truth Table
INx 0 1 SxA Off On SxB On Off
Table 10. ADG1434 LFCSP_VQ Truth Table
EN 1 0 0 INx X 0 1 SxA Off Off On
Rev. 0 | Page 9 of 20
SxB Off On Off
06181-006
S3A
D2 S2A IN2 IN3 S3A
6 7 8 9 10
ADG1433/ADG1434 TYPICAL PERFORMANCE CHARACTERISTICS
6 TA = 25C 5
7 6 5 4 3 2 1 0 -15 TA = +25C TA = +85C TA = -40C TA = +125C -10 -5 0 5 10 15
06181-010 06181-012
VDD = +15V VSS = -15V
ON RESISTANCE ()
4
3
2 VDD VDD VDD VDD VDD = +15V, VSS = -15V = +13.5V, VSS = -13.5V = +12V, VSS = -12V = +10V, VSS = -10V = +16.5V, VSS = -16.5V -8.5 -4.5 -0.5 3.5 7.5 11.5 15.5
06181-007
1
0 -16.5
-12.5
ON RESISTANCE ()
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 8. On Resistance as a Function of VD (VS), Dual Supply
9 TA = 25C 8
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures, 15 V Dual Supply
12 VDD = +5V VSS = -5V 10
7
ON RESISTANCE ()
ON RESISTANCE ()
6 5 4 3 2 1 0 -7 VDD VDD VDD VDD -6 = +7V, VSS = -7V = +5.5V, VSS = -5.5V = +5V, VSS = -5V = +4.5V, VSS = -4.5V
06181-008
8
6
4 TA = +25C TA = +85C TA = -40C TA = +125C -4 -3 -2 -1 0 1 2 3 4 5
06181-011
2
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
0 -5
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 9. On Resistance as a Function of VD (VS), Dual Supply
13 12 11 10 TA = 25C VSS = 0V
Figure 12. On Resistance as a Function of VD (VS) for Different Temperatures, 5 V Dual Supply
10 9 8
ON RESISTANCE ()
VDD = 12V VSS = 0V
ON RESISTANCE ()
9 8 7 6 5 4 3 2 1 0 0 VDD VDD VDD VDD VDD 1 = 12V = 13.2V = 10.8V = 8V = 5V 2 3 4 5 6 7 8 9 10 11 12 13
06181-009
7 6 5 4 3 2 1 0 0 TA = +25C TA = +85C TA = -40C TA = +125C 2 4 6 8 10 12
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 10. On Resistance as a Function of VD (VS), Single Supply
Figure 13. On Resistance as a Function of VD (VS) for Different Temperatures, 12 V Single Supply
Rev. 0 | Page 10 of 20
ADG1433/ADG1434
1600 70 60 50 40 30 20 ID, IS (ON) - - 0
06181-013
VDD = +15V 1400 VSS = -15V VBIAS = +10V/-10V
IDD PER CHANNEL TA = 25C
LEAKAGE CURRENT (pA)
1200 1000 800 600 400 IS (OFF) - + 200
ID, IS (ON) + + IS (OFF) + -
IDD (A)
VDD = +12V VSS = 0V
VDD = +15V VSS = -15V
10 0
VDD = +5V VSS = -5V 0 2 4 6 8 10 12 14
06181-015
06181-017 06181-016
-200
0
20
40
60
80
100
120
TEMPERATURE (C)
LOGIC, INx (V)
Figure 14. Leakage Currents as a Function of VD (VS), 15 V Dual Supply
1600
Figure 17. IDD vs. Logic Level
200 TA = 25C 150
CHARGE INJECTION (pC)
VDD = +5V 1400 VSS = -5V VBIAS = +4.5V/-4.5V
LEAKAGE CURRENT (pA)
1200 1000 800 600 400 200 0
ID, IS (ON) + +
100 50 0 -50 -100 -150 VDD = +15V VSS = -15V VDD = +5V VSS = -5V VDD = +12V VSS = 0V
IS (OFF) + -
ID, IS (ON) - -
0
20
40
60
80
100
120
06181-014
-200
IS (OFF) - +
-200 -15
-10
-5
0 VS (V)
5
10
15
TEMPERATURE (C)
Figure 15. Leakage Currents as a Function of Temperature, 5 V Dual Supply
2000 350 300 250
Figure 18. Charge Injection vs. Source Voltage
VDD = 12V 1800 VSS = 0V VBIAS = 1V/10V 1600
ID, IS (ON) + + ID, IS (ON) - -
LEAKAGE CURRENT (pA)
1400 1200 1000 800 600 400 200 0 -200 0 20 40 60 80
VDD = +5V VSS = -5V
VDD = +12V VSS = 0V
TIME (ns)
200 150 100 50 VDD = +15V VSS = -15V
IS (OFF) + -
IS (OFF) - + 100 120
06181-020
0 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 16. Leakage Currents as a Function of Temperature, 12 V Single Supply
Figure 19. Transition Time vs. Temperature
Rev. 0 | Page 11 of 20
ADG1433/ADG1434
0 -10 -20 VDD = +15V VSS = -15V TA = 25C 0.10 0.09 0.08 0.07 VDD = +5V, VSS = -5V, VS = +5V p-p LOAD = 110 TA = 25C
OFF ISOLATION (dB)
-30
-50 -60 -70 -80 -90 -100 10k 100k 1M 10M 100M
06181-018
THD + N (%)
-40
0.06 0.05 0.04 0.03 0.02 0.01 VDD = +15V, VSS = -15V, VS = +15V p-p
1G
100
1k FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 20. Off Isolation vs. Frequency
0 -10 -20 -30 VDD = +15V VSS = -15V TA = 25C 0
Figure 23. THD + N vs. Frequency
-20
VDD = +15V VSS = -15V TA = 25C V p-p = 0.63V
CROSSTALK (dB)
-40
-40
LOSS (dB)
-50 -60 -70 -80 -90 -100 10k 100k 1M 10M 100M 1G
06181-019
-60
NO DECOUPLING CAPACITORS
-80 DECOUPLING CAPACITORS ON SUPPLIES
-100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. Crosstalk vs. Frequency
0 -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 100 VDD = +15V VSS = -15V TA = 25C
Figure 24. ACPSRR vs. Frequency
LOSS (dB)
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 22. On Response vs. Frequency
06181-100
Rev. 0 | Page 12 of 20
06181-035
-110 1k
-120 100
06181-032
-110 1k
0 10
ADG1433/ADG1434 TEST CIRCUITS
V
IS (OFF)
S D IDS
06181-021
A VS
S
D
ID (OFF) A
06181-022
VS
VD
Figure 25. On Resistance
ID (ON) NC S D A
06181-023
Figure 26. Off Leakage
NC = NO CONNECT
VD
Figure 27. On Leakage
0.1F
VDD
VSS
0.1F
VIN
50%
50%
VDD VS SB SA IN VIN GND
VSS D RL 100 CL 35pF VOUT VIN 50% 90% 50% 90%
VOUT
tOFF
Figure 28. Switching Timing
0.1F
VDD
VSS
0.1F VIN
VDD VS SB SA IN VIN GND
VSS D RL 100 CL 35pF VOUT
VOUT 80%
tBBM
tBBM
06181-025
Figure 29. Break-Before-Make Delay
0.1F
VDD
VSS
0.1F 3V ENABLE DRIVE (VIN) VS 0V VOUT VOUT RL 100 CL 35pF OUTPUT 0V 0.9VO 50% 50%
VDD A2 A1 A0 EN VIN 50 GND
VSS S1A S1B D1
ADG1433
tOFF (EN)
0.9VO
06181-026
tON (EN)
Figure 30. Enable Delay, tON(EN), tOFF(EN)
Rev. 0 | Page 13 of 20
06181-024
tON
ADG1433/ADG1434
0.1F VDD VSS 0.1F VIN (NORMALLY CLOSED SWITCH)
VDD VS D IN VIN GND
VSS SB SA CL 1nF NC VOUT
ON
OFF
VIN (NORMALLY OPEN SWITCH) VOUT VOUT
Figure 31. Charge Injection
06181-027
QINJ = CL x VOUT
VDD 0.1F
VSS 0.1F NETWORK ANALYZER NC 50 VS
D
VDD 0.1F
VSS 0.1F
VDD SA
VSS SB
NETWORK ANALYZER VOUT RL 50
50
VDD SA
VSS
IN
D SB IN GND R 50
VIN GND
RL 50
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 32. Off Isolation
Figure 34. Channel-to-Channel Crosstalk
VDD 0.1F VSS 0.1F NETWORK ANALYZER NC 50 VS 50
VDD 0.1F
VSS 0.1F AUDIO PRECISION
VDD SA
VSS SB
VDD S IN
VSS
IN
RS VS V p-p
D
VIN GND RL 50 VOUT
D VIN GND
06181-029
RL 110
VOUT
06181-031
VOUT WITH SWITCH INSERTION LOSS = 20 log VOUT WITHOUT SWITCH
Figure 33. Bandwidth
Figure 35. THD + Noise
Rev. 0 | Page 14 of 20
06181-030
OFF ISOLATION = 20 log
VOUT VS
06181-028
VOUT VS
ADG1433/ADG1434 TERMINOLOGY
RON Ohmic resistance between Terminal D and Terminal S. RON The difference between the RON of any two channels. RFLAT(ON) The difference between the maximum and minimum value of on resistance as measured. IS (OFF) Source leakage current when the switch is off. ID (OFF) Drain leakage current when the switch is off. ID, IS (ON) Channel leakage current when the switch is on. VD (VS) Analog voltage on Terminal D and Terminal S. CS (OFF) Channel input capacitance for off condition. CD (OFF) Channel output capacitance for off condition. CD, CS (ON) On switch capacitance. CIN Digital input capacitance. tON(EN) Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF(EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANS Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. TBBM Off time measured between the 80% point of both switches when switching from one address state to another. VINL Maximum input voltage for Logic 0. VINH Minimum input voltage for Logic 1. IINL (IINH) Input current of the digital input. IDD Positive supply current. ISS Negative supply current. Off Isolation A measure of unwanted signal coupling through an off channel. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. AC Power Supply Rejection Ratio (ACPSRR) A measure of the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.
Rev. 0 | Page 15 of 20
ADG1433/ADG1434 OUTLINE DIMENSIONS
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 0.15 0.05 0.65 BSC 0.30 0.19 COPLANARITY 0.10 1.20 MAX
0.20 0.09
SEATING PLANE
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 36. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters
4.00 BSC SQ
0.60 MAX
12 13
0.50 0.40 0.30
PIN 1 INDICATOR
16
1
PIN 1 INDICATOR
3.75 BSC SQ 0.65 BSC TOP VIEW
9
EXPOSED PAD
4 8 5
2.65 2.50 SQ 2.35 0.25 MIN
1.95 BCS 0.80 MAX 0.65 TYP BOT TOM VIEW
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC.
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm, Very Thin Quad (CP-16-13) Dimensions shown in millimeters
Rev. 0 | Page 16 of 20
031006-A
12 MAX 1.00 0.85 0.80 SEATING 0.30 PLANE 0.23 0.18
0.05 MAX 0.02 NOM COPLANARITY 0.20 REF 0.08
ADG1433/ADG1434
6.60 6.50 6.40
20
11
4.50 4.40 4.30 6.40 BSC
1 10
PIN 1 0.65 BSC 0.15 0.05 COPLANARITY 0.10 0.30 0.19 1.20 MAX 0.20 0.09 8 0 0.75 0.60 0.45
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 38. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters
4.00 BSC SQ 0.60 MAX PIN 1 INDICATOR TOP VIEW 3.75 BCS SQ 0.75 0.55 0.35 0.05 MAX 0.02 NOM
0.60 MAX
16 15
PIN 1 INDICATOR
20 1
2.25 2.10 SQ 1.95
6 5
11 10
0.25 MIN 0.30 0.23 0.18
1.00 0.85 0.80 SEATING PLANE
12 MAX
0.80 MAX 0.65 TYP
0.50 BSC
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 39. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm x 4 mm Body, Very Thin Quad (CP-20-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG1433YRUZ 1 ADG1433YRUZ-REEL1 ADG1433YRUZ-REEL71 ADG1433YCPZ-REEL1 ADG1433YCPZ-REEL71 ADG1434YRUZ1 ADG1434YRUZ-REEL1 ADG1434YRUZ-REEL71 ADG1434YCPZ-REEL1 ADG1434YCPZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C
Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Thin Shrink Small Outline Package [TSSOP] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
EN Pin Yes Yes Yes Yes Yes No No No Yes Yes
Package Option RU-16 RU-16 RU-16 CP-16-13 CP-16-13 RU-20 RU-20 RU-20 CP-20-1 CP-20-1
Z = Pb-free part.
Rev. 0 | Page 17 of 20
ADG1433/ADG1434 NOTES
Rev. 0 | Page 18 of 20
ADG1433/ADG1434 NOTES
Rev. 0 | Page 19 of 20
ADG1433/ADG1434 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06181-0-10/06(0)
Rev. 0 | Page 20 of 20

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